In computer raster graphics machines, an image is typically displayed by raster scanning on a CRT display screen or other raster display view surface. Each minimum picture element at a display screen or view surface location is referred to as a pixel and each pixel is defined by one or more bits at one or more memory locations of the image data memory. In the simplest raster graphics display, the pixel at each display location is defined by one bit at a corresponding memory location of the image data memory.
The graphics image data memory is referred to as the image frame buffer, image refresh buffer or image bit map. The frame buffer is typically implemented by solid state random access memory (RAM) integrated circuit (IC) chips which may also constitute multiple memory banks. The frame buffer is referred to as a refresh buffer because the image frame on a CRT display screen is refreshed with the contents of the frame buffer, typically 30 or 60 raster cycles per second. The framebuffer is also referred to as a bit map because the contents or bits at the memory locations of the frame buffer are mapped onto the display screen or view surface by a raster scan generator. The contents of the frame buffer are organized in a linear stream by a video scan line generator to control CRT beam intensity.
Typically there is a fixed one to one correspondence between the memory address locations in the frame buffer and the pixel positions on the display screen or view surface identified as the user/viewer X,Y coordinate system. Where each pixel of the raster display view surface is defined by more than one bit for example 1, 2, 4, 8, or 16 bits, etc., the frame buffer memory locations are considered spatially organized into planes for example 1, 2, 4, 8, and 16 planes etc. corresponding to the multiple bits per pixel. The planes may be viewed as adding a third dimension to the bit map. The multiple bits per pixel bear a many-to-one correspondence with pixel positions of the user X,Y coordinate system view surface and are used to define color tone, gray scale, resolution, etc., and provide an image with greater definition.
The contents of the frame buffer are delivered to the video display section in a linear sequence by successive memory cycles. Successive memory cycles access the frame buffer in standard bit map word mode addressing or word configuration addressing of the multiple RAMs or memory banks constituting the frame buffer. Each memory cycle or memory access cycle accesses each of the memory banks consecutively and pulls out a sequence of bits from the successive RAMs or memory banks which may be visualized as a horizontal word or portion of a row of the standard bit map and a horizontal word or portion of a row of pixels on the user X,Y coordinate system view surface. Each scan line of the raster pattern is composed of a sequence of such words retrieved from the bit map forming complete rows or scan lines across the view surface. Typically, approximately half of the memory bandwidth or memory cycle time of the frame buffer is used for refresh memory access.
The other portion of the memory bandwidth or memory cycle time is available for updating the frame buffer or refresh buffer image memory. This is also referred to as writing, drawing or painting new images, image portions or image elements in the frame buffer. In the case of a CRT display, updating is typically accomplished by interleave during refresh. The new contents are displayed by refresh of the image on the display screen or view surface. A disadvantage of the conventional raster graphics word mode architecture and standard bit map is that the update of the frame buffer by "drawing" and "painting" is accomplished using the same word mode addressing and horizontal word configuration for accessing the multiple RAMs or memory banks. This is a disadvantage because the one-dimensional horizontal word mode or word configuration addressing, while it is adapted for efficiently accessing the contents of the frame buffer for refreshing the entire screen, cannot capitalize on the simple geometry of smaller two-dimensional areas of vectors to be drawn.
In vector drawing and painting only a defined portion of the frame buffer need be accessed for drawing, painting or modifying a small portion of the view surface area. The word mode addressing constrains the raster graphics machine to access numbers of memory locations far in excess of that required for a particular frame buffer update for example for drawing a vector. This is because the conventional word mode architecture and addressing looks only at long horizontal word sequences or row portions of the bit map in successive memory cycles. The vector or character to be drawn may conform more realistically to a small vertically oriented two-dimensional rectangle. Excessive time of multiple memory cycles is therefore required for updating the frame buffer in drawing and painting and the available frame buffer memory band width or available memory cycle time is inefficiently used.
The efficiency of performance of the raster graphics machine can be measured as a function of the number of bits defining pixels on the screen which are actually changed or updated each memory cycle. For example, if each memory cycle accesses 64 bits at 64 memory locations of the memory banks in the form of a 64 bit horizontal addressing word, then a 16 bit or 16 pixel vertical or diagonal vector is drawn or updated in the frame buffer inefficiently. In a single plane frame buffer perhaps only a single bit corresponding to a single pixel of the screen is updated each memory word access cycle. Therefore, up to 16 of the word memory access cycles may be required to complete the drawing of the vertical or diagonal vector updating only one bit each 64 bit word memory access cycle.
A cellular architecture for raster-scanned frame buffer displays is described by Satish Gupta and Robert F. Sproull of Carnegie-Mellon University and Ivan E. Sutherland in "A VLSI Architecture for Updating Raster-Scan Displays" Computer Graphics, Volume 15, Number 3, pp. 333-340, August 1981, also published in Proceedings of SIGGRAPH 81. pp. 71-78, Association of Computing Machinery, 1981. Gupta, Sproull, and Sutherland disclose an 8.times.8 bit cell organization of the frame buffer memory instead of the conventional horizontal word oriented memory organization for accessing the frame buffer by a single two-dimensional 8.times.8 bit cell configuration addressing mode.
According to this cell addressing concept, the frame buffer addressing and control circuits and bit map are designed to permit accessing successive memory address locations of the memory banks in a cell configuration corresponding to a square cell of pixels on the view surface or display screen. The cell configuration rectangle is composed of a similar number of bits or pixels as a horizontal word mode addressing word, for example 64 bits. However the cell addressing configuration viewed on the display screen or viewing surface is two-dimensional. As a result the frame buffer may be updated and a vertical or diagonal vector or two-dimensional character can be drawn in a reduced number of memory access cycles for updating or drawing the required bits and pixels. Vector drawing performance, which conventionally may be limited to one bit or pixel changed or updated per memory cycle, is upgraded to multiple bits or pixels changed or updated per memory access cycle.
The 8.times.8 cell addressing mode permits greater performance in number of pixels updated each memory access cycle when updating the frame buffer for drawing two-dimensional vectors, characters and bit block transfers. A disadvantage of the Gupta, Sproull, and Sutherland system however is that refresh of the display is less efficient than is the case with horizontal word mode addressing because the rectangular addressing mode cell must be used for refresh or display of the contents of the frame buffer across the view surface. Only one line of the 8.times.8 bit cell from each memory access cycle is used for assembling a particular refresh scan line. The Gupta et al. system architecture can achieve only one addressing mode and is constrained by the selected cell configuration and a bit map organization that permits only one addressing mode.
Another cell organized raster display architecture with a single 8.times.8 pixel cell is described by Jordan and Barrett in "A Cell Organized Raster Display for Line Drawings", CACM, Volume 17(2):70, February, 1974 and "A Scan Conversion Algorithm with Reduced Storage Requirements", CACM, 16 (11):676, November, 1973. Further background on computer graphics raster display frame buffer architecture is provided by Foley & Van Dam, Fundamentals of Interactive Computer Graphics, Addison-Wesley Company, Reading, Mass., 1982, Chapters 3, 10 and 12 et. seq. and Newman and Sproull, Principles of Interactive Computer Graphics, Second Edition, McGraw-Hill Book Company, New York, N.Y., 1979, Chapters 15-19. According to Foley and Van Dam the Tektronix 4025 and 4027 (Trademark) displays utilize cell encoding in which memory is allocated by storing cells of 8.times.14 pixels. In these prior references the architecture is limited to one addressing mode with a generally simple or straightforward standard or conventional bit map organization that can accommodate only one addressing mode cell configuration during frame buffer memory access cycles.
In the Texas Instrument TI 34010 Graphics System Processor or GSP, a different number of planes, for example 1, 2, 4, 8 or 16 planes, can be selected. This raster graphics system is therefore capable of defining pixels by different selected number of multiple bits. A different horizontal addressing word is associated with each different selection of number of planes. There are, therefore, different addressing words. A different but standard type bit map is associated with each selection of a different number of planes. However, once the number of planes and corresponding standard bit map is selected only one addressing word or mode is available.
Further discussion of the prior art and state of the art in raster addressing modes is found in applicant's Information Disclosure Statement along with discussion of distinguishing and contrasting features of the present invention. Applicant's Information Disclosure Statement and references cited are incorporated herein by reference.